View GX9533_49196.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GENLINX TMII GX9533
Serial Digital 8x9 Crosspoint
DATA SHEET FEATURES * operation beyond 622Mb/s * accepts SMPTE and PECL input levels * fully differential signal path * on-chip PECL current loads eliminate need for external pull-down resistors * capable of driving 100 differential loads * very low 500mW power consumption * additional expansion port input for construction of larger matrices * auxiliary monitoring output * easy to configure * double latched address inputs with separate load and configure * TTL/CMOS compatible control logic inputs * single 5V power supply APPLICATIONS Serial digital switching. video switching; datacom or telecom DESCRIPTION The GX9533 is a high speed 8x9 serial digital crosspoint. An expansion input port eases the design of larger switching matrices by reducing PCB layers and eliminating the need for cascaded secondary switching. Decode logic and double level latching to configure the matrix are included on chip. Separate LOAD and CONFIGURE inputs allow for asynchronous configuration and synchronous switching. These latches can also be made transparent for asynchronous switching by pulling the LOAD and CONFIGURE pins high. In the power saving (PS) mode, the GX9533 has a very low power consumption of 500mW. This is accomplished by driving a 400mV output swing into the on-chip 200 differential load termination in the expansion port of the next GX9533. This architecture provides a significant power savings and the elimination of external load resistors or impedance matching resistors. In applications where standard PECL levels are necessary, the GX9533 can be configured in "PECL Mode", to drive 800mV p-p into a 100 differential load. The power consumption in this mode increases to 860mW. ORDERING INFORMATION
PART NUMBER GX9533-CQY GX9533-CTY PACKAGE 100 pin MQFP Tray 100 pin MQFP Tape TEMPERATURE 0C to 70C 0C to 70C
GX9533
STD/PECL2 STD/PECL1 2 AUX IN 16 EXP0..7 16 IN0 .. 7 INPUT BUFFER 16 SWITCHING MATRIX OUTPUT BUFFER 16 AUX 2 2 VCCO OUT 0..7
CONFIG
CONFIG LATCH
LOAD LOAD A 3 OA0..2 IA0..3 4
LOAD LATCH VEE DECODE LOGIC VCC
BLOCK DIAGRAM
Revision Date: August 1999 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 521 - 41 - 03
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS = VCC-VEE) Input Voltage Range (any input) Power Dissipation VALUE 5.5V -0.3 to (VCC+0.3)V 975mW 0C to 70C -65C to +150C 260C
GX9533
Operating Temperature Range Storage Temperature Range Lead Temperature Range (soldering, 10 sec)
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0 to 70C unless otherwise shown.
PARAMETER Supply Voltage ECL Input Voltage Swing ECL Common Mode Input Voltage Range Logic Input Voltage High Low
CONDITION
MIN 4.75 200
TYP 5.0 800 -
MAX 5.25 1200 VCC-600 VCC 0.8
UNITS V mV p-p mV V V
with 1200mV input signal swing
2500 2.0 0
POWER SAVE 1 MODE
RSET = 4k
PARAMETER Supply Current Output Common Mode Voltage Output Voltage Swing Output Voltage High Low
CONDITION RL = 100
MIN VCC-1200 300 VCC-950 VCC-1400
TYP 115 450 -
MAX 150 VCC-800 600 VCC-600 VCC-1000
UNITS mA mV mV mV mV
POWER SAVE 2 MODE
RSET = 6k
PARAMETER Supply Current Output Common Mode Voltage Output Voltage Swing Output Voltage High Low
CONDITION RL = 200
MIN VCC-1200 300 VCC-950 VCC-1400
TYP 100 450 -
MAX 130 VCC-800 600 VCC-600 VCC-1000
UNITS mA mV mV mV mV
2
521 - 41 - 03
PECL MODE
RSET = 2k
PARAMETER Supply Current Output Common Mode Voltage Output Voltage Swing Output Voltage High Low
CONDITION RL = 100
MIN VCC-1450 700 VCC-1200 VCC-1850
TYP 170 800 -
MAX 185 VCC-1050 900 VCC-650 VCC-1450
UNITS mA mV mV mV mV
GX9533
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0 to 70C unless otherwise shown.
PARAMETER Maximum Input Data Rate Additive Jitter Standard Input Expansion Input Data In to Data Out Delay Standard Input Expansion Input Propagation Delay Match Standard Input Expansion Input CONFIGURE to Data Out Delay Main Out AUX Out LOAD/LOADA Pulse Width CONFIGURE Pulse Width IAN to LOAD/LOADA High Setup Time LOAD/LOADA to IAN Low Hold Time OAN to LOAD High Setup Time LOAD to OAN Low Hold Time LOAD High to CONFIGURE High Output Rise/Fall Time NOTE
SYMBOL
CONDITION For 90% eye opening 143 to 622 Mb/s, all hostile crosstalk
MIN -
TYP 850 80
MAX -
UNITS Mb/s ps p-p
-
70
-
ps p-p
tDLY
Average of all channels
-
1.7
-
ns
-
1.1
-
ns
-
350
-
ps
-
250
-
ps
tCD
-
10 11 700
-
ns ns ns ns ns ns ns ns ns ps
tLP tCP tILS tILH tOLS tOLH tLC
20 20 30 0 30 0 0 -
1. Use RMS addition to calculate additive jitter through cascaded devices.
3
521 - 41 - 03
PIN CONNECTIONS
STD/PECL2 AUX_IN AUX_IN
EXP0
EXP0
EXP1
EXP1
EXP2
EXP2
EXP3
EXP3
EXP4
EXP4
EXP5
EXP5
EXP6
EXP6
EXP7
EXP7
VCC
VCC
STD/PECL1 NC NC LOAD NC NC LOADA NC NC CNFG NC NC GX9533 TOP VIEW IA0 NC NC IA1 NC NC IA2 NC NC IA3 NC NC OA0 OA1 OA2 VEE AUX_OUT AUX_OUT
GX9533
IN0 IN0 VEE IN1 IN1 VEE IN2 IN2 VEE IN3 IN3 VEE IN4 IN4 VEE IN5 IN5 VEE IN6 IN6 VEE IN7 IN7 VEE VEE VCC VEE OUT0 OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
PIN DESCRIPTIONS
SYMBOL IN0 to IN7, IN0 to IN7 OUT0 to OUT7, OUT0 to OUT7 AUX_OUT, AUX_OUT AUX_IN, AUX_IN OA0 to OA2 IA0 to IA3 LOAD LOADA STD/ECL1, STD/ECL2 TYPE I O O I I I I I Differential data inputs. Differential data outputs. Auxiliary port output. Auxiliary port input. Output address select. Input address select. Loads input & output address. Loads auxiliary input address. Resistor connection for Power Save mode or PECL mode. Refer to Table 3. DESCRIPTION
4
521 - 41 - 03
OUT7
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
PIN DESCRIPTIONS
SYMBOL CNFG EXP0 to EXP7, EXP0 to EXP7 VCC VCCO VEE TYPE I I Switch configuration. Expansion port inputs. Positive power supply. DESCRIPTION
GX9533
Positive power supply (PECL outputs). Negative power supply.
8
Expan 7 sio Inputs n 6 5 4 3 2 1 0
Auxillia Inputry
0 1 2
Standa rd Inputs 3
IN
PU T
BU FF
0 1 4x1 2 Switch 3
ER S
4 5 6 7
4 5 4x1 6Switch 7
0
4x Sw 1 itch
1
3x Sw 1 itch
3x1 Switch
4 2 3
4x Sw 1 itch
5
6
7
Auxillia Outpury t
0
1
7 6 5 4 3 Main 2 Outputs
Fig. 1 Data Flow Diagram
100
90
% OPENING
80
70
60
50 700 800 900 1000 1100
BIT RATE (Mb/s)
Fig. 2 Typical Eye Opening vs. Bit Rate
5
521 - 41 - 03
DETAILED DESCRIPTION
DIFFERENTIAL INPUTS TABLE 1: Output Address Selection OA2 0 0 0 0 1
VCC INx GX9533 INx 1k
The inputs to the GX9533 will accept both SMPTE 259M as well as PECL input levels. The fully differential data path provides low jitter data rates of up to 700Mb/s.
0A1 0 0 1 1 0 0 1 1
0A0 0 1 0 1 0 1 0 1
OUTPUT PORT 0 1 2 3 4 5 6 7
GX9533
The main inputs (IN0..7) and expansion inputs (EXP0..7) are normally connected to a biased differential data source. The GX9533 inputs are not self biased, so unused inputs should be connected as shown in Figure 3 or Figure 4.
1 1 1
TABLE 2: Input Source Address Selection Fig. 3 Preferred Termination Of Unused Inputs IA3 0 0
INX GX9533 NC INX
IA2 0 0 0 0 1 1 1 1 0 1
IA1 0 0 1 1 0 0 1 1 X X
IA0 0 1 0 1 0 1 0 1 X X
INPUT PORT 0 1 2 3 4 5 6 7 EXP Quiet Mode
VCC
0 0 0 0 0 0
Fig. 4 Alternate Termination of Unused Inputs
Terminating the inputs as shown in Figure 3 will provide the highest noise immunity, since there is no possibility of noise coupling into the unconnected input pin.
I/O ADDRESS SELECTION
1 1
The GX9533 has a versatile LOAD/CONFIGURE architecture which simplifies IN/OUT switch configuration. An output is normally connected to an input by a two stage process:
Stage One: Loading The Configuration Into Latches
1. The output address is selected on the OA pins as shown in Table 1. 2. The input address is selected on the IA pins as shown in Table 2. 3. A LOAD pulse then transfers the output and input addresses into the GX9533 LOAD latch. The above three steps can be repeated up to eight times in order to configure the latch for all eight outputs. During step 3 above, if the LOADA pulse is also strobed, the latch is configured to connect the selected input to the ninth, auxiliary output.
Note that a QUIET mode is available as shown in Table 2. In QUIET mode, the outputs are latched in a DC state with OUTX = 1 and OUTX = 0.
Stage Two: Configuring The Matrix
A CONFIGURE strobe is applied to transfer the contents of the LOAD latch into the CONFIG latch. This action will cause the data flow through the GX9533 to be switched to the new configuration. Refer to Figure 6 for detailed timing information. Note that any single output can be asynchronously switched by having LOAD (or LOADA if desired) held high while CONFIG is strobed.
6
521 - 41 - 03
OUTPUT LEVEL SELECT
USING THE GX9533 TO EXPAND LARGER MATRICES The GX9533 pin-out and architecture provides a number of advantages over other crosspoint switches in the area of switching matrix board layout.
A single resistor, RSET, is used to set the amplitude of all differential outputs. Table 3 shows the value of RSET vs output drive capability.
TABLE 3: RSET vs VOUT
INPUTS 8-15
RSET 2k 4k 6k
VOUT (mV) 800 450 450
OUTPUT RL 100 100 200
MODE PECL Power Save 1 Power Save 2
GX9533
GX9533
GX9533
tDLY OUT0 to OUT7 OUT0 to OUT7
INPUTS 0-7
IN0 IN0
to IN7 to IN7
GX9533
GX9533
Fig. 5 GX9533 Data Latency
OUTPUTS 0-7 OUTPUTS 8-15
OAN, IAN
tLP
Fig. 9 Crosspoint Matrix Expansion - 16x16 Crosspoint Matrix BUS THROUGHTM PIN CONNECTIONS
LOAD/LOADA tILS tOLS tILH tOCH tCP CONFIGURE tLC
To easily facilitate a switching matrix design where inputs can be bussed across a matrix of crosspoint devices, Gennum's crosspoint device has "NC" pins opposite the input pins as shown by the dotted lines in the pin-out diagram above. This design allows bussing of inputs without having to use "vias" to get below the top layer of the printed circuit board.
EXPANSION PORT INPUT
Fig. 6 LOAD/LOADA and Configure Timing
The expansion inputs provide the following benefits: *
CONFIGURE tCD
by not having to run traces from the outputs of the crosspoint switch to a common output bus, crosstalk between output channels can be greatly reduced. fewer circuit board layers are required because the outputs of each device simply line up there are no transmission line effects caused by connecting High-Z outputs to an output bus because the output signal is being routed from the top of the switching matrix to the bottom through the devices, inputs can be simply bussed across the board without having to worry about input/output crosstalk.
OUT 0 TO OUT 7 OUT 0 TO OUT 7
*
Fig. 7 Configure to Data Out Delay
*
RSET STD/ECL2
*
STD/ECL1 GX9533
Fig. 8 GX9533 RSET Connection
7
521 - 41 - 03
PACKAGE DIMENSIONS
23.90 0.25 20.0 0.10 18.85 REF
GX9533
12 TYP 17.90 12.35 REF 14.0 0.10
0.25
0.75 MIN 0-7 0.30 MAX RADIUS
0- 7 0.13 MIN. RADIUS 1.95 REF 3.30 MAX
100 pin MQFP Dimensions in millimeters
0.80 0.10
0.65 BSC
0.30 0.08
2.80 0.25
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
REVISION NOTES:
Changes to document format.
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright April 1995 Gennum Corporation. All rights reserved. Printed in Canada.
521 - 41 - 03
8

▲Up To Search▲

Price & Availability of GX9533

	To Download GX9533 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .